1. Field of the Invention
The present invention relates to fabrication of a semiconductor device, and more particularly to a method for fabricating an SOI (Silicon On Insulator) substrate in which active and field regions are electrically isolated from each other by using a selective epitaxial-growth and a direct wafer bonding, and a method for fabricating a self-aligned bipolar transistor using the SOI substrate.
2. Description of the Prior Art
As integration of a semiconductor device is improved higher, there arises a difficult problem in design of a high-speed, high-frequency semiconductor device, or an integrated circuit using the high-frequency semiconductor device. For example, since a stray capacitance occurring between a substrate and a metal wiring portion formed thereon serves as a most dominant parasitic capacitance in such a high-frequency semiconductor device, operation speed of the device is seriously lowered due to occurrence of the stray capacitance and a signal attenuation is generated. The amount of a stray capacitance is generated in inverse proportion to the thickness of an insulating between the substrate and the metal wiring portion thereon. That is, the thinner the insulating layer formed therebetween becomes, the larger the amount of the stray capacitance becomes.
To minimize such a stray capacitance, a high-resistance substrate having a specific resistance of several M.OMEGA.cm or a semi-insulating semiconductor substrate such as a GaAs substrate has been used as a substrate of the high-frequency semiconductor device.
However, since the above-mentioned substrates are expensive, they are restrictively used in such a high-frequency semiconductor device. For this reason, a relatively inexpensive SOI substrate, which is composed of a silicon/insulator/silicon structure, has been mainly developed in the high-frequency semiconductor device.
In the SOI substrate, a buried insulating layer therein allows a stray capacitance occurring between the substrate and a metal wiring portion thereon to be lowered. If such an SOI substrate having a buried insulating layer is embodied in a semiconductor device, the operation speed of the device can be prevented from being lowered and occurrence of the signal attenuation can be restricted, as well-known in the art.
Prior art methods for fabricating an SOI substrate are broadly classified into an oxygen injection to a substrate and a direct substrate bonding. The former has an advantage that its sequence simplifies, and the latter has excellent advantages that adjustment of thickness of a buried oxide layer allows a stray capacitance to be further reduced, and particularly it is not necessary to perform a separate device isolation in case that an SOI substrate is embodied in an integrated circuit.
FIGS. 1A and 1B show the steps for fabricating an SOI substrate in accordance with the direct substrate bonding of the prior art fabricating methods.
Referring to FIG. 1A, first, by using a well-known photolithography, a singly crystal silicon substrate 11 is patterned to define active and inactive (i.e. field) regions and selectively etched back to form the active region 11b of a convex surface. Next, on overall surface of the substrate 11 an insulating layer 13 is deposited.
After formation of a polysilicon on the insulating layer a mechanical, chemical polishing is performed to form a planarized polysilicon layer 15, as shown in FIG. 1A.
In FIG. 1B, after bonding a bonding substrate 17 with the planarized polysilicon layer 15, polishing of the single crystal silicon substrate 11 is performed, whereby an SOI substrate is fabricated.
However, the direct bonding method for fabricating an SOI substrate is complicated in its fabrication sequence, and particularly it is necessary to perform an accurate planarization.
If an uniformly planarized surface can not be obtained during planarization, micro voids are generated between the polysilicon layer 15 and the bonding substrate 17 while bonding the bonding substrate 17 with the polysilicon layer 15, thereby resulting in lowering of a product quality.
Substantially, it is impossible to obtain a fully uniformly planarized surface of the polysilicon layer 19 by a well-known planarization in the art. It is because layers formed under the polysilicon layer 15 are not planarized. Specifically, since an area occupied by the active region 11b of the convex surface is relatively small, planarization of the polysilicon layer 15 is further lowered.
In the prior art method, the convex surface portion on the silicon substrate 11 is provided to control thickness of the active region 11b in accordance with a polishing speed difference between the silicon substrate 11 and the insulating layer 13.
On the other hand, in case that, after deposition of the insulating layer 13 without pattering the single crystal silicon substrate 11, the bonding substrate 17 is directly bonded with the silicon substrate, occurrence of micro voids can be somewhat reduced. Since the silicon substrate 11, however, must be polished to a certain thickness without a polishing stopper, it is difficult to control thickness of the active region and a uniformity thereof.
In addition, it is further difficult to make an active region having a uniformly planarized surface during fabrication of an SOI substrate capable of simultaneously performing a field isolation.